Impedance network design and its critical value prediction of tapped‐inductor single‐stage boost inverter

This study proposes a high inversion gain single‐stage boost inverter, which introduces a tapped inductor impedance network, including one tapped inductor and two diodes, to add to the front end of traditional voltage‐source inverter, called tapped‐inductor single‐stage boost inverter (TISSBI). The TISSBI has the merits of high inversion gain, common ground of input and dc‐bus, continuous input current and reduced capacitor voltage stress. This study also presents all the possible steady states of the TISSBI proposed. It is shown that, in addition to the desired three steady states, an operating cycle can contain another four abnormal states that do not contribute to the power conversion process. These four states can be avoided by selecting suitable value of capacitance and inductance. By using the equations derived in the steady‐state analysis, this study presents guidelines to design the impedance network accurately. Experimental results are provided to verify the effectiveness of the proposed circuit, the design method of impedance network and demonstrate the appearance of the four states when the capacitors and inductors are smaller than their critical values.