Open AccessAnalysis and discussion of false triggering of V ce desaturation protection circuit in a T‐type neutral point clamped inverter and its solutions
Author(s) -
Wu Yu,
Sun Yaojie,
Lin Yandan
Publication year - 2014
Publication title -
iet power electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.637
H-Index - 77
eISSN - 1755-4543
pISSN - 1755-4535
DOI - 10.1049/iet-pel.2013.0442
Subject(s) - inverter , insulated gate bipolar transistor , electrical engineering , antiparallel (mathematics) , voltage , electronic engineering , computer science , engineering , physics , quantum mechanics , magnetic field
IGBT in a T‐type inverter delivers unusual performance when accommodated with the conventional collector–emitter voltage ( V ce ) desaturation protection circuit. By analysing the switching behaviours in the corresponding control sequence, this study presents a false triggering failure phenomenon on the protection circuit. The phenomenon is theoretically analysed. It is aggravated at a larger load current and influenced by the capacitive effects in the antiparallel diode. Analysis done by the authors is validated in a three‐phase 15 kW T‐type inverter prototype. A false triggering of the protection circuit occurs when the current commutes among the insulated gate bipolar transistors (IGBTs) as a result of the IGBT characteristics being influenced. This study also puts forward a logic algorithm to provide guidance on hardware drive circuit or digital signal processor design depending on the analysis.