Operation method for parallel inverter system with common dc link | Zendy

Song Chunwei | Zendy; Zhao Rongxiang | Zendy; Zhu Minglei | Zendy; Zeng Zheng | Zendy

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Operation method for parallel inverter system with common dc link

Author(s) -

Song Chunwei,

Zhao Rongxiang,

Zhu Minglei,

Zeng Zheng

Publication year - 2014

Publication title -

iet power electronics

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.637

H-Index - 77

eISSN - 1755-4543

pISSN - 1755-4535

DOI - 10.1049/iet-pel.2013.0411

Subject(s) - inverter , robustness (evolution) , gate array , computer science , electronic engineering , voltage , current loop , control theory (sociology) , digital signal processor , digital control , field programmable gate array , control system , digital signal processing , engineering , computer hardware , electrical engineering , control (management) , biochemistry , chemistry , artificial intelligence , gene

The configuration of parallel inverter system (PIS) with common dc link and no isolation measure is proposed. The gate control signals for switches in parallel inverters are synchronised to achieve ideal parallel operation status. Adopting the double loop control method which is composed of an outer voltage loop and an inner current loop, PIS has good dynamic response and robustness. In addition, the circulating current caused by the delay time of control signal transmission is studied in detail. The proposed operation method is easy to be implemented on the digital control board using digital signal processing and field‐programmable gate array. The simulation and experimental results are presented to demonstrate the validity and features of the proposed operation method.

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