Open AccessRobust phase locked‐loop algorithm for single‐phase utility‐interactive inverters
Author(s) -
Elrayyah Ali,
Sozer Yilmaz,
Elbuluk Malik
Publication year - 2014
Publication title -
iet power electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.637
H-Index - 77
eISSN - 1755-4543
pISSN - 1755-4535
DOI - 10.1049/iet-pel.2013.0351
Subject(s) - robustness (evolution) , phase locked loop , harmonics , control theory (sociology) , voltage sag , grid , computer science , frequency grid , transient (computer programming) , algorithm , swell , loop (graph theory) , electronic engineering , voltage , engineering , mathematics , power quality , telecommunications , physics , biochemistry , geometry , control (management) , jitter , thermodynamics , combinatorics , electrical engineering , gene , artificial intelligence , chemistry , operating system
An accurate, robust and efficient transport‐delay based phase‐lock loop (TDPLL) algorithm is proposed for single phase utility interactive inverters. The traditional TDPLL has low complexity and its transient response is smooth, but its performance is significantly affected by the change in the grid frequency. The proposed TDPLL is designed to have robustness against grid frequency variations. The proposed method uses two delays instead of one to cancel the grid frequency variation effect. Since the grid voltage could be polluted by harmonics and may suffer from sag/swell anomalies, the proposed method is enhanced further to be robust against these sources of disturbances. Moreover, a method is proposed to tune the parameters of the system. The performance of the proposed PLL is validated through simulations and experimental results.