Open AccessAsymmetrical multilevel converter topology with reduced number of components
Author(s) -
Babaei Ebrahim,
Farhadi Kangarlu Mohammad,
Hosseinzadeh Mohammad Ali
Publication year - 2013
Publication title -
iet power electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.637
H-Index - 77
eISSN - 1755-4543
pISSN - 1755-4535
DOI - 10.1049/iet-pel.2012.0497
Subject(s) - topology (electrical circuits) , computer science , mathematics , combinatorics
In this study, firstly a new basic unit is proposed for multilevel converters. The proposed basic units are used as building blocks to form a cascaded multilevel converter. In other words, the proposed topology consists of cascaded basic units. The proposed basic unit and the proposed multilevel converter use lower number of switching devices and gate driver circuits. In the proposed topology, two design parameters are available: the number of cascaded basic units and the number of dc voltage sources in each basic unit. These two parameters can be used to design the desired multilevel converter based on the operational conditions. Therefore the proposed topology offers good flexibility in designing. An algorithm for determining the values of the dc voltage sources is given in order to generate maximum number of voltage levels. The comparison results with some recently introduced topologies show that the proposed topology effectively reduces the components count. The simulation results obtained in PSCAD/EMTDC as well as the experimental results of a 51‐level inverter based on the proposed topology are presented to verify its performance.