Open AccessAnalysis and implementation of an interleaved series input parallel output active clamp forward converter
Author(s) -
Chen ShinJu,
Yang SungPei,
Cho MengFu
Publication year - 2013
Publication title -
iet power electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.637
H-Index - 77
eISSN - 1755-4543
pISSN - 1755-4535
DOI - 10.1049/iet-pel.2011.0438
Subject(s) - leakage inductance , converters , inductance , ripple , transformer , capacitor , voltage , forward converter , voltage spike , electronic engineering , computer science , clamper , boost converter , electrical engineering , topology (electrical circuits) , engineering
A novel dual active clamp forward topology with interleaved series input parallel output (ISIPO) structure is proposed here. The ISIPO active clamp forward converter enables the converter cells to share the input voltage and output current. The interleaved operation can diminish the output current ripple in the output capacitor. The output capacitance of switching devices and the resonant inductance are utilised to realise the resonance at the transition interval of switches such that the zero‐voltage‐switching operation for all switches can be achieved. Moreover, the energy stored in the transformer leakage inductance is recycled such that the voltage stresses of switching devices are reduced. All these features make the proposed converter suitable for the DC–DC converters with high input voltage, high output current and high‐efficiency applications. The operating principle and design considerations are provided in detail. Finally, experimental results based on a 240 W(12 V/20 A) prototype with an input voltage of 400 V are presented to verify the theoretical analysis and circuit performance.