Open AccessDesign of integer‐ N PLL frequency synthesiser for E‐band frequency for high phase noise performance in 5G communication systems
Author(s) -
Berber Zakia,
Kameche Samir,
Benkhelifa Elhadj
Publication year - 2020
Publication title -
iet networks
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.466
H-Index - 21
ISSN - 2047-4962
DOI - 10.1049/iet-net.2018.5245
Subject(s) - dbc , phase noise , phase locked loop , voltage controlled oscillator , pll multibit , frequency synthesizer , jitter , frequency offset , frequency divider , frequency multiplier , bandwidth (computing) , electrical engineering , electronic engineering , physics , acoustics , telecommunications , engineering , voltage , cmos , orthogonal frequency division multiplexing , channel (broadcasting)
A phase‐locked loop (PLL) frequency synthesiser is designed for 5G E‐band frequency. ADF4155‐PLL chip with an external (loop filter, prescaler, VCO and an external reference oscillator) is simulated using the ADIsimPLL tool. With a third‐order passive filter having 1 MHz loop bandwidth and 45° phase margin, simulation results show that the proposed synthesiser achieves a total phase noise (PN) of −81.50 and −115.7 dBc/Hz at 100 kHz and 10 MHz, respectively, for (71–76 GHz) and −80.39 and −114.7 dBc/Hz at 100 kHz and 10 MHz, respectively, for the highest (81–86 GHz) 5G frequency range even if −160 dBc/Hz VCO noise floor and −170dBc/Hz reference PN floor are integrated in the design. Also, the performance of the system in terms of RMS jitter and reference spurs are verified. The proposed synthesiser for 5G application presents very low reference spurs (−113, −112 dBc) at 50 MHz offset frequency and low RMS jitter (0.39, 0.40 ps) for 70 and 80 GHz frequency band, respectively.