Open AccessFully integrated fractional‐N phase‐locked loop for GNSS standards
Author(s) -
Ghattan Kashani Zahra,
Izadi Avanji Seyed Amin
Publication year - 2019
Publication title -
iet microwaves, antennas and propagation
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.555
H-Index - 69
eISSN - 1751-8733
pISSN - 1751-8725
DOI - 10.1049/iet-map.2018.5528
Subject(s) - dbc , gnss applications , phase noise , offset (computer science) , phase locked loop , cmos , voltage , electrical engineering , delay locked loop , physics , power (physics) , control theory (sociology) , engineering , electronic engineering , computer science , global positioning system , telecommunications , control (management) , quantum mechanics , artificial intelligence , programming language
This study presents the design of a fully integrated fractional‐N phase‐locked loop (FNPLL) for the Global Navigation Satellite System (GNSS) applications. A new linearisation technique is presented for a charge pump (CP) circuit to improve the mismatch between the charging and discharging currents. The linearised currents help to reduce the static phase offset and the reference spurs of the FNPLL and the constant current helps to control the PLL dynamics precisely. The presented FNPLL is designed in a 0.18 µm CMOS technology. The simulation result reveals that the linearity of the CP is enhanced greatly when the technique is enabled and the current mismatch is <0.2 µA over the output voltage ranging from 0.2 to 1.65 V. The phase noise of the FNPLL at 10 and 100 KHz offset frequencies without the linearised CP are −85 and −90 dBc/Hz, respectively, and with the high linear CP are −90 and −97 dBc/Hz, respectively. The output power spectral density of the FNPLL shows that the power of the highest fractional spur is about −57 dBc. The lock time and the power consumption of the designed FNPLL are 50 µs and 11 mW from a 1.8 V power supply, respectively.