Open AccessAbout 250/285 GHz push–push oscillator using differential gate equalisation in digital 65‐nm CMOS
Author(s) -
Fahs Bassem,
Wu Kefei,
Aouimeur Walid,
Mansha Muhammad Waleed,
Gaquière Christophe,
Gamand Patrice,
Knap Wojciech,
Hella Mona M.
Publication year - 2019
Publication title -
iet microwaves, antennas and propagation
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.555
H-Index - 69
eISSN - 1751-8733
pISSN - 1751-8725
DOI - 10.1049/iet-map.2018.5308
Subject(s) - dbc , phase noise , voltage controlled oscillator , vackář oscillator , cmos , electrical engineering , variable frequency oscillator , optoelectronics , digitally controlled oscillator , materials science , physics , local oscillator , engineering , voltage
This study presents a push–push oscillator architecture based on differential gate equalisation to enhance the oscillation frequency while providing relatively high output power with ultra‐compact layout form factor. The frequency enhancement is derived as a function of the equivalent RLC model of the oscillator's main constituents. The proposed principle is applied to a terahertz oscillator in the 200–300 GHz range to mitigate the excessive substrate and skin effect losses in standard digital 65‐nm complementary metal–oxide–semiconductor technology at such high frequencies. The design concept is validated using two single‐stage push–push oscillators. The first oscillator shows −8.1 dBm output power at 250 GHz oscillation frequency and −106.8 dBc/Hz phase noise at 10 MHz offset while consuming 76 mW power from 1.5 V DC supply voltage. The chip area is 200 × 250 μm 2 . The second oscillator provides −14.8 dBm output power at 285 GHz and −106 dBc/Hz phase noise at 10 MHz offset with 80 mW power consumption from 1.5 V DC supply. The chip area is 200 × 200 μm 2 .