Open AccessLow‐latency median filter core for hardware implementation of 5 × 5 median filtering
Author(s) -
Kumar Vineet,
Asati Abhijit,
Gupta Anu
Publication year - 2017
Publication title -
iet image processing
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.401
H-Index - 45
eISSN - 1751-9667
pISSN - 1751-9659
DOI - 10.1049/iet-ipr.2016.0737
Subject(s) - median filter , field programmable gate array , latency (audio) , computer science , filter (signal processing) , low latency (capital markets) , computer hardware , architecture , core (optical fiber) , embedded system , real time computing , telecommunications , artificial intelligence , computer vision , computer network , image processing , art , visual arts , image (mathematics)
This study presents hardware implementation of 5 × 5 median filter that uses a new low‐latency median filter (LLMF) core in order to find the median of 25 integer values. The proposed LLMF core architecture computes the median of 25 integers in just three clock cycles. The maximum frequency of operation of the proposed median filter architecture is 394 MHz on the Xilinx Zynq FPGA device. The proposed LLMF core provides reduced clock cycle latency compared with the existing state‐of‐the‐art median filter core architectures.