Open AccessHardware efficient multiplier‐less multi‐level 2D DWT architecture without off‐chip RAM
Author(s) -
Wu Changkun,
Zhang Wei,
Jia Qi,
Liu Yanyan
Publication year - 2017
Publication title -
iet image processing
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.401
H-Index - 45
eISSN - 1751-9667
pISSN - 1751-9659
DOI - 10.1049/iet-ipr.2016.0695
Subject(s) - multiplier (economics) , computer science , chip , architecture , parallel computing , system on a chip , computer hardware , computer architecture , embedded system , arithmetic , mathematics , telecommunications , economics , macroeconomics , art , visual arts
This study presents a multi‐level 2D discrete wavelet transform (DWT) architecture without off‐chip RAM. Existing architectures use one off‐chip RAM to store the image data, which increases the complexity of the system. For one‐chip design, line‐based architecture based on modified lifting scheme is proposed. By replacing the multipliers with canonic sign digit multipliers, a critical path of one full‐adder delay is achieved. As per theoretical estimate, for three‐level 2D DWT with an image of N × N size, the proposed architecture requires 123 adders, 66 subtracters, 167 registers, temporal memory of 7.5 N words and input RAM of 3 N bytes. The estimated hardware requirement shows that for the image size of 512 × 512 and three‐level DWT, the proposed architecture involves at least 14.1% less transistor‐delay‐product than existing architectures.