Open AccessLow‐cost and high‐speed hardware implementation of contrast‐preserving image dynamic range compression for full‐HD video enhancement
Author(s) -
Li ShihAn,
Tsai ChiYi
Publication year - 2015
Publication title -
iet image processing
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.401
H-Index - 45
eISSN - 1751-9667
pISSN - 1751-9659
DOI - 10.1049/iet-ipr.2014.0162
Subject(s) - computer science , field programmable gate array , computer hardware , throughput , frame rate , data compression , process (computing) , pixel , computer vision , telecommunications , wireless , operating system
This study presents a cost‐efficient and high‐performance field programmable gate array (FPGA)‐based hardware implementation of a contrast‐preserving image dynamic range compression algorithm, which is an important function used in modern digital video cameras and displays to improve visual quality of standard dynamic range colour images (8 bits/channel). To achieve this purpose, a hardware‐friendly approximation to an existing fast dynamic range compression with local contrast preservation (FDRCLCP) algorithm is proposed. The computation of the proposed approximated FDRCLCP algorithm requires only fixed‐point unsigned binary addition, multiplication, and bit‐shifting. Moreover, the proposed hardware implementation uses a line buffer instead of a frame buffer to process whole image data. These advantages significantly improve throughput performance and reduce memory requirement of the system. The FPGA implementation of the proposed algorithm requires only about 98 K bits on‐chip memory and achieves about 170.24 MHz operating frequency by using an Altera Cyclone II device. This is a large improvement compared with the existing results as it is quick enough to process full high‐definition videos (1920 × 1080 pixels) at least 80 frames per second using a low‐cost FPGA device.