High throughput and energy efficient two‐dimensional inverse discrete cosine transform architecture

This study presents an energy efficient and high throughput two‐dimensional inverse discrete cosine transform (IDCT) architecture, suitable for high speed and high quality image and video processing applications. The proposed architecture is based on the Arai–Agui–Nakajima IDCT algorithm. The high throughput rate is accomplished through the high degree of pipelining in the multipliers of the architecture. The distribution properties of the input signal, that is, the high percentage of zero coefficients, are exploited in order to lower power consumption. In particular, whenever an all zero column enters the architecture, the corresponding pipeline stages are adjacently deactivated in order to lower switching activity. Furthermore, a novel approach, regarding the transposition structure, is introduced. The all zero columns are not loaded in the transposition memory. Instead, they are encoded through a single bit in a parallel data path, thereby reducing the power consumption of the transposition process by 19%. The proposed architecture, implemented in a 65 nm field programmable gate array, provides a throughput rate of 2.722 Gpixel/s for a power consumption of 0.831 W. The experimental results and the comparison with previous work validate the efficiency and the suitability of the proposed implementation for high speed and high quality video decoding applications.