Open AccessHardware stream cipher with controllable chaos generator for colour image encryption
Author(s) -
Barakat Mohamed L.,
Mansingka Abhinav S.,
Radwan Ahmed G.,
Salama Khaled N.
Publication year - 2014
Publication title -
iet image processing
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.401
H-Index - 45
eISSN - 1751-9667
pISSN - 1751-9659
DOI - 10.1049/iet-ipr.2012.0586
Subject(s) - stream cipher , computer science , encryption , field programmable gate array , cipher , chaotic , chaos (operating system) , block cipher mode of operation , generator (circuit theory) , computer hardware , cryptography , throughput , pixel , shift register , self shrinking generator , stream cipher attack , running key cipher , algorithm , computer vision , artificial intelligence , wireless , engineering , telecommunications , electrical engineering , computer network , computer security , wind power , power (physics) , quantum mechanics , induction generator , physics , chip
This study presents hardware realisation of chaos‐based stream cipher utilised for image encryption applications. A third‐order chaotic system with signum non‐linearity is implemented and a new post processing technique is proposed to eliminate the bias from the original chaotic sequence. The proposed stream cipher utilises the processed chaotic output to mask and diffuse input pixels through several stages of XORing and bit permutations. The performance of the cipher is tested with several input images and compared with previously reported systems showing superior security and higher hardware efficiency. The system is experimentally verified on XilinxVirtex 4 field programmable gate array (FPGA) achieving small area utilisation and a throughput of 3.62 Gb/s.