Open AccessFast and automatic security test on cryptographic ICs against fault injection attacks based on design for security test
Author(s) -
Shao Cuiping,
Li Huiyun,
Zhou Jianbin
Publication year - 2017
Publication title -
iet information security
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.308
H-Index - 34
eISSN - 1751-8717
pISSN - 1751-8709
DOI - 10.1049/iet-ifs.2016.0203
Subject(s) - cryptography , computer science , fault injection , embedded system , automatic test pattern generation , cryptographic primitive , test (biology) , workload , fault coverage , fault (geology) , reliability engineering , computer security , cryptographic protocol , engineering , electronic circuit , software , operating system , electrical engineering , paleontology , seismology , geology , biology
Fault injection attacks have constituted a serious threat against cryptographic integrated circuits (ICs). However, the security test nowadays is just sample test with workload statistics and experiences as the qualitative criterion, and results in costly, time‐consuming and error‐prone test procedures. This study presents a design for security test (DFST) method for cryptographic ICs against fault injection attacks. The DFST involves identifying the sensitive registers for various crypto modules, inserting the scan chains and generating the specific test patterns for security test. Then the security test is conducted on the manufactured cryptographic ICs with the industrial automatic test equipment. With this DFST method, a fast and automatic security test can be applied onto volume production of cryptographic ICs. Experimental results on an RSA implementation demonstrate the validity of this method.