Open AccessHigh‐performance and high‐speed implementation of polynomial basis Itoh–Tsujii inversion algorithm over GF(2 m )
Author(s) -
Rashidi Bahram,
Rezaeian Farashahi Reza,
Sayedi Sayed Masoud
Publication year - 2017
Publication title -
iet information security
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.308
H-Index - 34
eISSN - 1751-8717
pISSN - 1751-8709
DOI - 10.1049/iet-ifs.2015.0461
Subject(s) - trinomial , polynomial basis , finite field , field programmable gate array , exponentiation , critical path method , gf(2) , computation , multiplier (economics) , mathematics , algorithm , parallel computing , computer science , polynomial , discrete mathematics , computer hardware , mathematical analysis , systems engineering , engineering , economics , macroeconomics
In this study high‐performance and high‐speed field‐programmable gate array (FPGA) implementations of polynomial basis Itoh–Tsujii inversion algorithm (ITA) over GF(2 m ) constructed by irreducible trinomials and pentanomials are presented. The proposed structures are designed by one field multiplier and k ‐times squarer blocks or exponentiation by 2 k , where k is a small positive integer. The k ‐times squarer blocks have an efficient tree structure with low critical path delay, and the multiplier is based on a proposed high‐speed digit‐serial architecture with minimum hardware resources. Furthermore, to reduce the computation time of ITA, the critical path of the circuit is broken to finer path using several registers. The computation times of the structure on Virtex‐4 FPGA family are 0.262, 0.192 and 0.271 µs for GF(2 163 ), GF(2 193 ) and GF(2 233 ), respectively. The comparison results with other implementations of the polynomial basis Itoh–Tsujii inversion algorithm verify the improvement in the proposed architecture in terms of speed and performance.