Open AccessPerformance analysis of a multilevel inverter based shunt active filter with RT‐EMD control technique under ideal and non‐ideal supply voltage conditions
Author(s) -
Dash Ashish Ranjan,
Panda Anup Kumar,
Lenka Rajesh Kumar,
Patel Ranjeeta
Publication year - 2019
Publication title -
iet generation, transmission and distribution
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.92
H-Index - 110
eISSN - 1751-8695
pISSN - 1751-8687
DOI - 10.1049/iet-gtd.2018.7060
Subject(s) - control theory (sociology) , voltage , inverter , harmonics , matlab , computer science , controller (irrigation) , hilbert–huang transform , filter (signal processing) , engineering , electronic engineering , algorithm , control (management) , electrical engineering , artificial intelligence , agronomy , computer vision , biology , operating system
In this study, a real‐time empirical mode decomposition (RT‐EMD) based control technique is adopted for effective mitigation of system harmonics under ideal and non‐ideal supply voltage conditions. The proposed control algorithm takes the active component of load current samples and the positive sequence voltage component for generating the desired reference. The fundamental component of load current is found by employing RT‐EMD, which decomposes the distorted non‐linear sample into a finite number of fine‐scale signals termed as intrinsic mode function (IMF). Each IMF is extracted adopting continuous calculation of upper and lower envelopes using a series pipeline structure which decreases the computational complexity. The proposed control algorithm takes the positive sequence voltage component for generating the desired reference so that the system can operate in non‐sinusoidal grid voltage conditions. The proposed control algorithm adopts carrier‐based modulation scheme for switching of the inverter module. The effectiveness of the proposed control approach is investigated in MATLAB‐Simulink environment with balanced and unbalanced loading condition and its experimental validation is carried out by a hardware prototype model using a Spartan 6 FPGA controller.