Open AccessPrototyping and hardware‐in‐loop verification of OCR
Author(s) -
Kumar Praveen,
Kumar Vishal,
Pratap Rajendra
Publication year - 2018
Publication title -
iet generation, transmission and distribution
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.92
H-Index - 110
eISSN - 1751-8695
pISSN - 1751-8687
DOI - 10.1049/iet-gtd.2017.1268
Subject(s) - computer science , emulation , relay , verilog , computer hardware , interfacing , field programmable gate array , overcurrent , inrush current , embedded system , vhdl , transformer , electronic engineering , power (physics) , engineering , electrical engineering , voltage , physics , quantum mechanics , economics , economic growth
This study presents the design and development of a soft‐core prototype of an overcurrent relay (OCR). The prototype is implemented on the field programmable gate array and its functionality has been verified using hardware‐in‐loop testing on the real‐time digital simulator. Computational efficiency and memory requirement of the OCR is improved by using integer arithmetic Verilog design platform. Extreme inverse and very inverse characteristics of the OCR based on standard inverse‐time characteristics as per IEEE standard C37.112‐1996 is used and tested in the proposed design. Digital design of the proposed algorithm, emulation results, complete hardware setup and experimental test results are presented in this study. The performance of the OCR is evaluated for a large range of characteristic parameters (pick‐up current and time‐dial setting) and various operating conditions which validate the operation of the relay in real time with the power network. The designed relay has the ability to differentiate between fault and inrush current to avoid any mal‐operation during energisation of transformers.