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Synchronisation mechanism and interfaces design of multi‐FPGA‐based real‐time simulator for microgrids
Author(s) -
Li Peng,
Wang Zhiying,
Wang Chengshan,
Fu Xiaopeng,
Yu Hao,
Wang Liwei
Publication year - 2017
Publication title -
iet generation, transmission and distribution
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.92
H-Index - 110
eISSN - 1751-8695
pISSN - 1751-8687
DOI - 10.1049/iet-gtd.2016.1552
Subject(s) - field programmable gate array , microgrid , interfacing , computer science , real time simulation , embedded system , interface (matter) , benchmark (surveying) , real time digital simulator , converters , co simulation , hardware in the loop simulation , power (physics) , computer hardware , electric power system , physics , control (management) , geodesy , bubble , quantum mechanics , artificial intelligence , maximum bubble pressure method , parallel computing , geography
Real‐time simulation of a microgrid involving massive high‐frequency power electronic converters, various distributed generators and energy storage systems is computationally demanding. Due to the prominent computing resources and high speed communication, field programmable gate arrays (FPGAs) can be used together to realise the real‐time simulation of a microgrid. For a complete multi‐FPGA‐based real‐time simulator, interfaces are essential to communicate with each other and with different types of apparatus. The internal interfaces between FPGAs make it possible to operate in parallel, sharing the computational burden. External interfaces between an FPGA and physical devices contribute to the implementation of hardware‐in‐the‐loop simulation. In this study, interfacing techniques including multi‐FPGA system topology determination, time‐step synchronisation mechanism and precise communication are proposed in detail. An analogue‐to‐digital and digital‐to‐analogue interface is designed to facilitate physical connections to external devices. A modified microgrid benchmark with photovoltaics and a battery is simulated with a time‐step of 3 μs on a 4‐FPGA‐based real‐time simulator. Simulation results are compared with PSCAD/EMTDC to validate the interface design.

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