Open AccessSynchronisation and anti‐synchronisation of chaotic systems with application to DC–DC boost converter
Author(s) -
Sakthivel Rathinasamy,
Santra Srimanta,
Marshal Anthoni Selvaraj,
Kuppili Venkatanareshbabu
Publication year - 2017
Publication title -
iet generation, transmission and distribution
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.92
H-Index - 110
eISSN - 1751-8695
pISSN - 1751-8687
DOI - 10.1049/iet-gtd.2016.0971
Subject(s) - control theory (sociology) , lyapunov function , sampling (signal processing) , chaotic , controller (irrigation) , linear matrix inequality , computer science , function (biology) , set (abstract data type) , mathematics , mathematical optimization , control (management) , nonlinear system , physics , filter (signal processing) , quantum mechanics , artificial intelligence , evolutionary biology , agronomy , computer vision , biology , programming language
This study addresses the design of sampled‐data feedback L ∞ controller for synchronisation of chaotic systems with external disturbances. By employing a novel time‐dependent Lyapunov function which is positive definite at sampling times but not necessary between the sampling times, a new set of sufficient conditions in terms of linear matrix inequality is derived to a design sampled‐data L ∞ control for synchronisation. More precisely, the proposed synchronisation results depend on both the lower and upper bounds on sampling interval and also the available information of the actual sampling pattern is fully used. Further, based on the Lyapunov function, an asymptotic anti‐synchronisation criterion is derived by analysing the corresponding anti‐synchronisation error systems. Subsequently, a set of sampled‐data synchronisation control is designed in terms of solution to certain matrix inequalities that can be solved effectively by using available software. Finally, a numerical example based on boost converter DC–DC model is employed to show the effectiveness of the proposed sampled‐data L ∞ synchronisation and anti‐synchronisation control scheme.