Open AccessFPGA‐based real‐time implementation of a direct torque control with second‐order sliding mode control and input–output feedback linearisation for an induction motor drive
Author(s) -
Krim Saber,
Gdaim Soufien,
Mtibaa Abdellatif,
Faouzi Mimouni Mohamed
Publication year - 2020
Publication title -
iet electric power applications
Language(s) - English
Resource type - Journals
ISSN - 1751-8679
DOI - 10.1049/iet-epa.2018.5829
Subject(s) - direct torque control , control theory (sociology) , vector control , field programmable gate array , torque , stator , space vector modulation , computer science , controller (irrigation) , induction motor , engineering , inverter , control engineering , control (management) , embedded system , physics , artificial intelligence , voltage , electrical engineering , thermodynamics , mechanical engineering , agronomy , biology
A robust direct torque control (DTC) strategy for an induction motor is proposed in this study. In fact, the proposed control strategy is defined by a combination of DTC, space vector modulation (SVM), input–output feedback linearisation (IOFL), a second‐order super‐twisting speed controller (STSC), and sliding‐mode‐load torque and stator‐flux observers with stator resistance estimation. First, non‐linear IOFL is suggested to achieve decoupled flux and torque control, and the SVM technique is utilised to control the inverter switching frequency which decreases the torque ripples and noise. Second, to improve the speed regulation, an STSC is added to an SVM‐DTC‐IOFL scheme. Furthermore, the sliding mode observers of the stator flux and of the load torque are proposed in order to improve the control performances by reducing uncertainties and to prevent the effects of the stator resistance variations. Indeed, this study presents the importance of implementing the suggested SVM‐DTC‐IOFL using a field‐programmable gate array (FPGA) circuit. The main interest of the FPGA implementation is the decrease in the control loop delay, due to the parallel processing offered by the FPGA. The performances of the proposed control algorithm are investigated by digital simulation using a Xilinx system generator tool and experimental implementation utilising FPGA‐Virtex‐5‐ML507.