Open AccessThreshold‐voltage‐drift‐aware scheduling for belief propagation decoding of LDPC‐coded NAND flash memory
Author(s) -
Liu Wenjie,
Han Guojun,
Fan Zhengqin,
Fang Yi,
Cai Guofa
Publication year - 2019
Publication title -
iet communications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.355
H-Index - 62
eISSN - 1751-8636
pISSN - 1751-8628
DOI - 10.1049/iet-com.2019.0110
Subject(s) - low density parity check code , computer science , decoding methods , nand gate , scheduling (production processes) , real time computing , algorithm , logic gate , mathematics , mathematical optimization
With the continual increase of storage density, NAND flash memory cells are particularly vulnerable to channel noise, which significantly degrades the storage reliability. To overcome this issue, low‐density parity check (LDPC) codes have been considered as a preferable choice for flash memory systems. To further improve the efficiency of the decoder, the convergence speed and the error‐rate performance are the key performance indicators for LDPC‐coded NAND flash memory. In this study, a threshold‐voltage‐drift‐aware scheduling for belief propagation (BP) decoding of LDPC‐coded NAND flash memory is introduced to improve the convergence speed and the error‐rate performance. The basic idea of the proposed scheduling is to find an appropriate updated order of variable nodes according to their corresponding locations of threshold voltages. Since the proposed scheduling updates less reliable variable nodes with higher priority, it can improve the efficiency of BP decoding. Simulation results show that the proposed scheduling not only significantly improves the convergence speed, but also obtains better error‐rate performance than the conventional serial scheduling.