High‐throughput and compact reconfigurable architectures for recursive filters

This study presents various high‐throughput reconfigurable architectures and their hardware implementation characteristics for infinite impulse response (IIR) filters. It is known that finite word length effects can be alleviated, to some extent, by realising a high‐order IIR filter using the cascade of lower‐order filter sections. The authors utilise the cascade structure of the first‐order and second‐order filters and apply a set of optimisation techniques, such as cutset retiming, look‐ahead transformations, and interleaving for high‐throughput realisations of IIR filters. Since the cascade structure may require a relatively large number of computational resources and storage elements, which depends linearly on the number of sections, the authors also present a filter processor architecture for the compact implementation of IIR filters. Filter architectures are developed in the fully parameterisable fixed‐point representation and verified against their synthesisable Verilog descriptions. The authors present the implementation results of the transformed filter architectures on a Xilinx Virtex‐7 field‐programmable gate array (FPGA). To the best of their knowledge, this is the first presentation of various high‐throughput and compact IIR filter architectures and their FPGA implementation characteristics.