Open AccessAlgorithm and FPGA implementation of interpolation‐based soft output MMSE MIMO detector for 3GPP LTE
Author(s) -
Salari Amin,
Fakhraie Sied Mehdi,
Abbasfar Aliazam
Publication year - 2014
Publication title -
iet communications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.355
H-Index - 62
eISSN - 1751-8636
pISSN - 1751-8628
DOI - 10.1049/iet-com.2013.0279
Subject(s) - mimo , computer science , detector , algorithm , field programmable gate array , orthogonal frequency division multiplexing , interpolation (computer graphics) , mimo ofdm , minimum mean square error , virtex , channel (broadcasting) , electronic engineering , mathematics , telecommunications , computer hardware , engineering , frame (networking) , statistics , estimator
The number of orthogonal frequency division multiplexing (OFDM) sub‐carriers in modern wireless communication systems such as Third Generation Partnership Project (3GPP) long term evolution (LTE) can be as high as 2048. Channel matrix of data sub‐carriers in conventional multiple‐input–multiple‐output (MIMO) receivers is derived by interpolating channel matrix of pilot sub‐carriers and MIMO detection is performed on each interpolated channel matrix. Symbol detection on sub‐carrier by sub‐carrier basis demands a very high computational power. This study presents the first very‐large scale integration implementation of a novel 4 × 4 interpolation‐based soft output minimum‐mean‐squared error (MMSE) MIMO detector which combines channel estimation and MIMO detection. The detector computes MMSE matrix on pilot sub‐carriers using proposed division‐free matrix inversion algorithm and obtains MMSE matrix of data sub‐carriers by interpolation, reducing computational complexity by more than 66%. The throughput of the implemented detector on Virtex‐7 field programmable gate array (FPGA) exceeds 1 Gbps with 2.1 µs latency.