Open AccessEfficient VLSI architectures of lifting based 3D discrete wavelet transform
Author(s) -
Basiri M. Mohamed Asan
Publication year - 2020
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/iet-cdt.2020.0038
Subject(s) - very large scale integration , discrete wavelet transform , computer science , lifting scheme , throughput , field programmable gate array , cmos , wavelet , parallel computing , second generation wavelet transform , daubechies wavelet , computer hardware , data compression , wavelet transform , embedded system , algorithm , electronic engineering , artificial intelligence , engineering , telecommunications , wireless
Discrete wavelet transform (DWT) is widely used in the image and video compression due to its high compression ratio and resolution. This study proposes efficient very large scale integration (VLSI) architectures of lifting based 3D‐DWT using (5,3) and (9,7) Daubechies wavelets. The advantage of these proposed architectures is the absence of storage buffer in between the row, column, and temporal processes. Also, five and nine numbers of frames of the 3D signal can be processed in parallel using the proposed (5,3) and (9,7) lifting based DWTs, respectively. Due to this parallelism and the elimination of storage buffers, the throughput of the proposed design is greater than other existing techniques. The authors have implemented all the existing and proposed 3D‐DWTs using 45 nm CMOS library with Cadence and Artix‐7 FPGA with Xilinx Vivado. The synthesis results show that the proposed designs achieve significant improvement in throughput than various existing designs. For example, the proposed (9,7) lifting based 3D‐DWT achieves 85.4% of improvement in the throughput than the conventional design.