Open AccessAutomated planning for finding alternative bug traces
Author(s) -
Jana Rajib Lochan,
Dey Soumyajit,
Mondal Arijit,
Dasgupta Pallab
Publication year - 2020
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/iet-cdt.2019.0283
Subject(s) - computer science , software engineering , task (project management) , microprocessor , root cause , debugging , software bug , systems engineering , engineering , programming language , reliability engineering , software , embedded system
Bug traces serve as references for patching a microprocessor design after a bug has been found. Unless the root cause of a bug has been detected and patched, variants of the bug may return through alternative bug traces, following a different sequence of micro‐architectural events. To avoid such a situation, the verification engineer must think of every possible way in which the bug may return, which is a complex problem for a modern microprocessor. This study proposes a methodology which gleans high‐level descriptions of the micro‐architectural steps and uses them in an artificial Intelligence planning framework to find alternative pathways through which a bug may return. The plans are then translated to simulation test cases which explore these potential bug scenarios. The planning tool essentially automates the task of the verification engineer towards exploring possible alternative sequences of micro‐architectural steps that may allow a bug to return. The proposed methodology is demonstrated in three case studies.