Open AccessHetro8T: power and area efficient approximate heterogeneous 8T SRAM for H.264 video decoder
Author(s) -
Bharti Pramod Kumar,
Suraeelam,
Mekie Joycee
Publication year - 2019
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/iet-cdt.2019.0019
Subject(s) - static random access memory , computer science , video decoder , decoding methods , video quality , embedded system , computer hardware , truncation (statistics) , real time computing , algorithm , metric (unit) , operations management , machine learning , economics
Wide‐spread availability of high‐speed INTERNET and rapid increase of smart‐phone users have significantly increased online video surfing. Video decoders like H.264/H.265/MPEG consume a significant amount of power in Static Random Access Memory (SRAM) buffers. In this study, the authors propose a 1 kb (32 × 32) heterogeneous 8T SRAM architectures with (2‐lower order bits) and without truncation for H.264 video decoder. They have used heterogeneous sized SRAM design and bit‐truncation techniques are used simultaneously to obtain low power memory design for the H.264 video decoder. They show that the proposed approximate memory used for H.264 video decoder provide high video quality even at low power and low area budget of 0.3 µW/pixel and 5.2 µm 2 /pixel, respectively, at 0.5 V and 20 MHz in UMC 28 nm CMOS technology. The proposed memory architecture is compared with existing approximate memories such as heterogeneous 6T, hybrid 8T/6T, all‐identical 6T, and all‐identical 8T SRAM memory. The results show that proposed memory architectures perform cumulatively better than existing techniques in terms of dynamic power, leakage power, and area.