Mitigating information leakage during critical communication using S*FSM

Security‐centric components and systems, such as System‐on‐Chip early‐boot communication protocols and ultra‐specific lightweight devices, require a departure from minimalist design constructs. The need for built‐in protection mechanisms, at all levels of design, is paramount to providing cost‐effective, efficient, secure systems. In this work, Securely derived Finite State Machines (S*FSM) and power‐aware S*FSM are proposed and studied. Overall results show that to provide an S*FSM, the typical FSM requires a 50% increase in the number of states and a 57% increase in the number of product terms needed to define the state transitions. These increases translate to a minimum encoding space increase of 70%, raising the average encoding length from 4.8 bits to 7.9 bits. When factoring in relaxed structural constraints for power and space mitigation, the respective increases of 53 and 67% raise the average number of bits needed to 7.3 and 7.9. Regarding power savings, current minimisation is possible for both FSMs and S*FSMs through the addition of encoding constraints with average current reductions of 30 and 70%, respectively. Overall, a power‐constrained S*FSM consumes about 5% more power than insecure FSMs with binary encodings, though with a penalty of a 95% increase in layout area.