Open AccessEffect of NBTI stress on DSP cores used in CE devices: threat model and performance estimation
Author(s) -
Kachave Deepak,
Sengupta Anirban,
Neema Shubha,
Sri Harsha Panugothu
Publication year - 2018
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
ISSN - 1751-861X
DOI - 10.1049/iet-cdt.2018.5081
Subject(s) - negative bias temperature instability , digital signal processing , degradation (telecommunications) , stress (linguistics) , reliability (semiconductor) , electronic engineering , reliability engineering , computer science , engineering , voltage , threshold voltage , electrical engineering , power (physics) , transistor , physics , linguistics , philosophy , quantum mechanics
Device aging is a critical failure mechanism in nanoscale designs. Prolonged device degradation may result in failure. Delay degradation of a design depends on various factors such as threshold voltage, temperature, input vector pattern and so on. An attacker who is aware of this phenomenon may exploit by accelerating the performance degradation mechanism. This study proposes a novel reliability and threat analysis of negative bias temperature instability (NBTI) stress on digital signal processing (DSP) cores. The main contributions of this study are as follows: (a) identifying input vectors that cause maximum degradation of DSP cores due to NBTI stress, (b) analysing impact of NBTI stress for varying stress time on DSP core in terms of delay degradation and (c) analysing performance comparison of stress versus no‐stress condition for various input vector samples.