Open AccessRadix‐4 3 based two‐dimensional FFT architecture with efficient data reordering scheme
Author(s) -
S. Kala,
Mathew Jimson,
Jose Babita R.,
S. Nalesh
Publication year - 2019
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
ISSN - 1751-861X
DOI - 10.1049/iet-cdt.2018.5075
Subject(s) - fast fourier transform , computer science , field programmable gate array , parallel computing , twiddle factor , split radix fft algorithm , computation , digital signal processing , application specific integrated circuit , signal processing , computational science , algorithm , computer hardware , fourier transform , mathematics , fourier analysis , mathematical analysis , short time fourier transform
Multi‐dimensional Discrete Fourier Transforms (DFTs) play an important role in signal and image processing applications. Image reconstruction is a key component in signal processing applications like medical imaging, computer vision, face recognition etc. Two dimensional fast Fourier Transform (2D FFT) and Inverse FFT plays vital role in reconstruction. In this paper we present a fast 64 × 64 point 2D FFT architecture based on radix‐43 algorithm using a parallel unrolled radix‐4 3 FFT as the basic block. Our radix‐4 3 architecture is a memory optimized parallel architecture which computes 64‐point FFT, with least execution time. Proposed architecture produces reordered output of both 64‐point one dimensional (1D) FFT and 64 × 64 point 2D FFT, without using any additional hardware for reordering. The proposed architecture has been implemented in UMC 40nm CMOS technology with clock frequency of 500 MHz and area of 0.841 mm 2 . The power consumption of proposed architecture is 358 mW at 500 MHz. Energy efficiency (FFTs computed per unit of energy) is 341 points/Joule. Computation time of 64 × 64 point FFT is 8.19 μs. ASIC implementation results shows better performance of proposed work in terms of computation time when compared with state‐of‐art implementation. Proposed architecture has also been implemented in Virtex‐7 FPGA which gives comparable area.