Open AccessEfficient composition of scenario‐based hardware specifications
Author(s) -
Gennaro Alessandro,
Stankaitis Paulius,
Mokhov Andrey
Publication year - 2019
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
ISSN - 1751-861X
DOI - 10.1049/iet-cdt.2018.5073
Subject(s) - computer science , reuse , scalability , concurrency , high level synthesis , overhead (engineering) , automation , composition (language) , embedded system , distributed computing , computer architecture , field programmable gate array , database , programming language , engineering , mechanical engineering , linguistics , philosophy , waste management
Complex hardware systems can be designed by breaking down their behaviour into high‐level descriptions of constituent scenarios and then composing these scenarios into an efficient hardware implementation using a form of high‐level synthesis. There are a few existing methodologies for such scenario‐based specification and synthesis, and in this study, the authors focus on highly concurrent systems, whose scenarios are typically described using explicit concurrency models such as partial orders. They propose a new algorithm for the composition of partial order scenarios. Unlike previously published methods, the proposed algorithm supports composition constraints , which allow the designer to restrict certain aspects of the composition in order to reuse legacy intellectual property (IP). Furthermore, the authors implementation is more scalable and can cope with specifications comprising hundreds of scenarios at the cost of only ≃ 5 % of area overhead compared to optimal solutions obtained by the exhaustive search. The proposed algorithm is implemented in an open‐source electronic design automation (EDA) tool, validated on a set of benchmarks, and compared to the state‐of‐the‐art behavioural composition approaches and to other existing methodologies that make use of behavioural synthesis.