Open AccessYield modelling and analysis of bundled data and ring‐oscillator based designs
Author(s) -
Zhang Yang,
Li Ji,
Cheng Huimei,
Zha Haipeng,
Draper Jeffrey,
Beerel Peter A.
Publication year - 2019
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/iet-cdt.2018.5040
Subject(s) - ring oscillator , monte carlo method , yield (engineering) , limit (mathematics) , chip , electronic circuit , computer science , electronic engineering , combinational logic , margin (machine learning) , ring (chemistry) , sensitivity (control systems) , logic gate , mathematics , algorithm , engineering , statistics , electrical engineering , cmos , materials science , telecommunications , chemistry , organic chemistry , metallurgy , machine learning , mathematical analysis
The ill effects of process, voltage, and temperature variations are significantly reduced by ring‐oscillator (OR)‐based clocks and bundled‐data (BD) designs. Such designs include delay lines that enable the addition of test margin that can either by set uniformly across all manufactured chips or tuned individually per‐chip. This study mathematically analyses the resulting yield subject to a limit on shipped product quality providing a practical mechanism of optimising the test margins for these circuits. The model also provides a means of quantifying the benefits from the correlation in the delay line and combinational logic. In particular, using correlation values obtained from Monte Carlo analysis of a sample circuit in a 65 nm process, the model shows that BD and OR‐based circuits can have an over 50% yield advantage over their synchronous counterparts.