Open AccessDesign of an extended 2D mesh network‐on‐chip and development of A fault‐tolerantrouting method
Author(s) -
Kurokawa Yota,
Fukushi Masaru
Publication year - 2019
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
ISSN - 1751-861X
DOI - 10.1049/iet-cdt.2018.5032
Subject(s) - computer science , static routing , multipath routing , network on a chip , link state routing protocol , latency (audio) , distributed computing , deadlock , routing (electronic design automation) , dynamic source routing , computer network , architecture , mesh networking , policy based routing , parallel computing , embedded system , routing protocol , telecommunications , art , visual arts , wireless
This paper proposes an extended two‐dimensional mesh Network‐on‐Chip architecture for region‐based fault tolerant routing methods. The proposed architecture has an additional track of links and switches at the four sides of a mesh network so that it can partially reconfigure the network around faulty regions to provide new detour paths. This allows to simplify the complex routing rules of the existing fault‐tolerant routing methods and avoid long detour routing paths. Modified routing method is also proposed for the new architecture and the deadlock freeness is proved. Simulation results show that the proposed architecture with the modified routing method reduces the average communication latency by about 39% compared to the existing state‐of‐the‐art method at the expense of low hardware overhead.