Open AccessHigh performance and predictable memory controller for multicore mixed‐criticality real‐time systems
Author(s) -
Dabaghi Arezoo,
Farbeh Hamed
Publication year - 2019
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
ISSN - 1751-861X
DOI - 10.1049/iet-cdt.2018.5031
Subject(s) - predictability , computer science , multi core processor , memory controller , embedded system , controller (irrigation) , criticality , suite , key (lock) , mixed criticality , computer architecture , parallel computing , operating system , semiconductor memory , history , physics , archaeology , quantum mechanics , nuclear physics , agronomy , biology
Multicore processors are widely used in today's real‐time embedded systems to satisfy the performance and predictability requirements as well as reduce cost. A vast majority of multicore embedded systems are running several tasks with mixed‐criticality, in which the non‐functional requirements of the tasks are different or even conflicting. A major challenge in mixed‐criticality systems is to maximise the efficiency of shared resources while satisfying the criticality requirements. Shared memory is a key component that should be well managed and memory controller plays the main role in this case. Several memory controllers have been introduced in the literature for multicore processors. In this article, the authors performed a deep investigation on three state‐of‐the‐art memory controllers using gem5 full‐system simulator and Xilinx ISE Design Suite, and compared them in terms of predictability and performance. Then, the authors proposed a memory controller that provides the same predictability as the most predictable existing controller while improving the performance by 12.3%.