Open AccessHardware variant NSP with security‐aware automated preferential algorithm
Author(s) -
Paul Rourab,
Sikder Gitesh,
Chakrabarti Amlan,
Ghosh Ranjan
Publication year - 2018
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
ISSN - 1751-861X
DOI - 10.1049/iet-cdt.2018.0006
Subject(s) - computer science , field programmable gate array , encryption , throughput , cipher , hash function , embedded system , flexibility (engineering) , key (lock) , cryptography , suite , computer hardware , algorithm , computer network , operating system , computer security , statistics , mathematics , archaeology , wireless , history
Efficient and cost‐effective hardware design of network security processor (NSP) is of vital importance in the present era due to the increasing need of security infrastructure in a wide range of computing applications. Here, the authors propose an NSP in field programmable gate array (FPGA) platform where according to a strict power, throughput, resource, and security priorities, a proposed preferential algorithm chooses a cipher suite to program the hardware. The choice is based on a rank list of available cipher suites depending on efficient system index evaluated in terms of power, throughput, resource, and security data and their given weights by the user. Encryption, hash, and key exchange algorithm along with their architectural variants serve excellent hardware flexibility whose bit files are stored in secure digital memory. The proposed design used an isolated key memory where secret keys are stored in encrypted form along with the hash value. The design is implemented using ISE14.4 suite with ZYNQ7z020‐clg484 FPGA platform. The performances of the variants architecture of the crypto algorithms are considerably better in terms of power, throughput, and resource than the existing works reported in the literature.