Open AccessRole of circuit representation in evolutionary design of energy‐efficient approximate circuits
Author(s) -
Mrazek Vojtech,
Vasicek Zdenek,
Hrbacek Radek
Publication year - 2018
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/iet-cdt.2017.0188
Subject(s) - adder , computer science , electronic circuit , benchmark (surveying) , evolutionary algorithm , circuit design , scalability , key (lock) , representation (politics) , efficient energy use , mathematical optimization , computer engineering , mathematics , artificial intelligence , engineering , embedded system , electrical engineering , telecommunications , computer security , geodesy , database , politics , law , geography , political science , latency (audio)
Circuit approximation has been introduced in recent years as a viable method for constructing energy‐efficient electronic systems. An open problem is how to effectively obtain approximate circuits showing good compromises between key circuit parameters – the error, power consumption, area and delay. The use of evolutionary algorithms in the task of circuit approximation has led to promising results. Unfortunately, only relatively small circuit instances have been tackled because of the scalability problems of the evolutionary design method. This study demonstrates how to push the limits of the evolutionary design by choosing a more suitable representation on the one hand and a more efficient fitness function on the other hand. In particular, the authors show that employing full adders as building blocks leads to more efficient approximate circuits. The authors focused on the approximation of key arithmetic circuits such as adders and multipliers. While the evolutionary design of adders represents a rather easy benchmark problem, the design of multipliers is known to be one of the hardest problems. The authors evolved a comprehensive library of energy‐efficient 12‐bit multipliers with a guaranteed worst‐case error. The library consists of 65 Pareto dominant solutions considering power, delay, area and error as design objectives.