Open AccessImplementation of nMPRA CPU architecture based on preemptive hardware scheduler engine and different scheduling algorithms
Author(s) -
Zagan Ionel,
Găitan Vasile Gheorghiţă
Publication year - 2017
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
ISSN - 1751-861X
DOI - 10.1049/iet-cdt.2017.0163
Subject(s) - computer science , scheduling (production processes) , fixed priority pre emptive scheduling , embedded system , architecture , fair share scheduling , real time operating system , real time computing , rate monotonic scheduling , operating system , engineering , schedule , art , operations management , visual arts
Taking into consideration the requirements of real‐time embedded systems, the processor scheduler must guarantee a constant scheduling frequency, providing determinism and predictability of tasks execution. The purpose of this study is to implement the nMPRA (multi pipeline register architecture) processor into field‐programmable gate array, and to integrate the already existing scheduling methods, thus providing a preemptive schedulability analysis of the proposed architecture based on the pipeline assembly line and hardware scheduler. This study describes a hardware implementation of the real‐time scheduler named nHSE (hardware scheduler engine for n tasks) and presents the results obtained using the appropriate schedulability methods used in real‐time environments. The scheduling and task switch operations are the main source of non‐determinism, being successfully dealt with real‐time nMPRA concept, in order to improve the system's functionality. Some mechanisms used for synchronisation and inter‐task communication are also taken into consideration.