Open AccessUnified multi‐objective mapping for network‐on‐chip using genetic‐based hyper‐heuristic algorithms
Author(s) -
Xu Changqing,
Liu Yi,
Li Peng,
Yang YinTang
Publication year - 2018
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/iet-cdt.2017.0156
Subject(s) - computer science , latency (audio) , algorithm , heuristic , reduction (mathematics) , genetic algorithm , energy consumption , convergence (economics) , mathematics , engineering , artificial intelligence , machine learning , telecommunications , geometry , economic growth , electrical engineering , economics
In this study, a flexible energy‐ and delay‐aware mapping approach is proposed for the co‐optimisation of energy consumption and communication latency for network‐on‐chips (NoCs). A novel genetic‐based hyper‐heuristic algorithm (GHA) is proposed as the core algorithm. This algorithm consists of bottom‐level optimisation which includes a variety of operators and top‐level optimisation which selects suitable operators through a ‘reward’ mechanism. As this algorithm can select suitable operators automatically during the mapping process, it noticeably improves convergence speed and demonstrates excellent stability. Compared to the random algorithm, GHA can achieve on average 23.28% delay reduction and 11.81% power reduction. Compared to state‐of‐the‐art mapping algorithms, GHA produces improved mapping results with less time, especially when the size of NoC is large.