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Sign detector for the extended four‐moduli set { 2 n − 1 , 2 n + 1 , 2 2 n + 1 , 2 n + k }
Author(s) -
Hiasat Ahmad
Publication year - 2018
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/iet-cdt.2017.0088
Subject(s) - detector , adder , moduli , sign (mathematics) , carry (investment) , arithmetic , set (abstract data type) , residue number system , mathematics , reduction (mathematics) , algorithm , computer science , electronic engineering , physics , engineering , cmos , telecommunications , mathematical analysis , geometry , finance , quantum mechanics , economics , programming language
This work is an additional effort to improve the performance of a four‐moduli set residue‐based sign detector. The study proposes an arithmetic sign detector for the extended four‐moduli set { 2 n − 1 , 2 n + 1 , 2 2 n + 1 , 2 n + k } , where n and k are positive integers such that 0 ≤ k ≤ n . The proposed arithmetic unit is built using carry‐save adders and carry‐generation circuits. When compared with the only sign detector available in the literature for a similar moduli set, the proposed one showed very slight reductions in area and power. However, it showed a huge reduction in time delay. Using very‐large‐scale integration tools, the presented sign detector achieved a reduction of (48.8–59.2)% in time delay.

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