Open AccessQuadruple throughput fixed point quarter precision multiply accumulate circuit design
Author(s) -
Mohamed Asan Basiri M.,
Noor Mohammad S.k.
Publication year - 2017
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/iet-cdt.2017.0051
Subject(s) - throughput , very large scale integration , computer science , multiplier (economics) , cmos , parallel computing , computer hardware , embedded system , electronic engineering , wireless , engineering , telecommunications , economics , macroeconomics
This study proposes an efficient very large scale integration (VLSI) architecture for quadruple throughput fixed point multiply accumulate circuit (MAC). The proposed n × n bits MAC is used to perform one n × n bits or two n × ( n /2) bits or four ( n /2) × ( n /2) bits MAC operations in parallel. The objective of the proposed MAC is to improve throughput of the existing MAC designs. The proposed and existing designs are implemented by 45 nm CMOS TSMC library and the results show that the proposed architecture achieves better improvement in throughput than existing designs. For example, the proposed 32 × 32 bits MAC architecture achieves 60.4% of improvement in throughput over existing array multiplier‐based double throughput MAC.