Open Access65‐nm CMOS low‐energy RNS modular multiplier for elliptic‐curve cryptography
Author(s) -
Asif Shahzad,
Andersson Oskar,
Rodrigues Joachim,
Kong Yinan
Publication year - 2018
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/iet-cdt.2017.0017
Subject(s) - elliptic curve cryptography , modular arithmetic , chinese remainder theorem , residue number system , modular exponentiation , computer science , dissipation , cryptography , cmos , application specific integrated circuit , modular design , elliptic curve digital signature algorithm , nist , energy consumption , parallel computing , embedded system , algorithm , electronic engineering , public key cryptography , engineering , electrical engineering , physics , encryption , operating system , natural language processing , thermodynamics
Modular multiplication (MM) is the main operation in cryptography algorithms such as elliptic‐curve cryptography (ECC) and Rivest–Shamir–Adleman, where repeated MM is used to perform elliptic curve point multiplication and modular exponentiation, respectively. The algorithm for the proposed architecture is derived from the Chinese remainder theorem and performs MM completely within a residue number system (RNS). Moreover, a 40‐channel RNS moduli‐set is proposed for this architecture to benefit from the short‐channel width of the RNS moduli‐set. The throughput of the architecture is enhanced by pipelining and pre‐computations. The proposed architecture is fabricated as an ASIC using 65‐nm CMOS technology. The measurement results are obtained for energy dissipation at different voltage levels from 0.43 to 1.25 V. The maximum throughput of the proposed design is 1037 Mbps while operating at a frequency of 162 MHz with an energy dissipation of 48 nJ. The proposed architecture enables the construction of low‐voltage and energy‐efficient ECCs.