Open AccessReducing bypass‐based network‐on‐chip latency using priority mechanism
Author(s) -
Noghondar Amir Fadakar,
Reshadi Midia,
Bagherzadeh Nader
Publication year - 2018
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
ISSN - 1751-861X
DOI - 10.1049/iet-cdt.2016.0161
Subject(s) - network on a chip , computer science , latency (audio) , router , computer network , interconnection , scalability , multi core processor , core router , network topology , embedded system , distributed computing , parallel computing , operating system , telecommunications
In the movement from a multi‐core to a many‐core era, cores count on the chip increases quickly thus interconnect plays a large role in achieving the desired performance. Network‐on‐chip (NoC) is the most widely used interconnect as a scalable alternative for traditional shared bus in many‐core chips. As the dimensions of mesh‐based NoC increase, routers and links serve as a major part to achieve the desired performance and low‐latency communication between cores. In this study, the authors propose an arbitration mechanism for NoC that leads to a reduction in congestion delay in routers as well as the network latency. The proposed mechanism is compatible with the bypass and baseline pipeline in routers. System simulations with Noxim demonstrate reduction in latencies and power consumption using different routing algorithms for 4×4,8×8 and 16×16 mesh topologies, as compared with a baseline router.