Open AccessFinite state machine‐based fault tolerance technique with enhanced area and power of synthesised sequential circuits
Author(s) -
ElMaleh Aiman H.
Publication year - 2017
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/iet-cdt.2016.0085
Subject(s) - fault tolerance , finite state machine , sequential logic , state (computer science) , power (physics) , fault (geology) , electronic circuit , computer science , fault coverage , reliability engineering , algorithm , engineering , logic gate , electrical engineering , physics , quantum mechanics , seismology , geology
Recently, a finite state machine‐based fault tolerance technique for sequential circuits based on protecting few states with high probability of occurrence has been proposed. In this study, the authors propose an algorithm that starts with a given state assignment targeting the optimisation of either area or power and generates a state assignment that preserves the original state assignment and satisfies the fault tolerance requirements for the protected states. Experimental results demonstrate the effectiveness of the proposed algorithm in significantly reducing the area and power of synthesised sequential circuits while enhancing their fault tolerance.