Open AccessFPGA implementation of hardware efficient adaptive filter robust to impulsive noise
Author(s) -
Parmar Chintan A.,
Ramanadham Bhaskar,
Darji Anand D.
Publication year - 2017
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/iet-cdt.2016.0067
Subject(s) - field programmable gate array , vhdl , adaptive filter , computer science , electronic engineering , noise (video) , computer hardware , embedded system , real time computing , algorithm , engineering , artificial intelligence , image (mathematics)
Adaptive filters are prevalent in many real‐time signal processing applications. Many adaptive algorithms already exist, but most of them assume white Gaussian noise as disturbance. However, for many applications such as electrocardiogram, foetus heart rate measurement, low frequency atmospheric noise, underwater acoustic noise and signal measurement in instrumentation, the impulsive noise is more common. This study presents a modified robust mixed norm (MRMN) adaptive filter algorithm robust to impulsive noise with higher convergence rate and lower steady state error (SSE). MRMN adaptive filter algorithm has been simulated using Matlab and Xilinx system generator high level synthesis tool and a significant improvement in SSE and convergence speed is obtained compared with the existing adaptive filter algorithms for similar specifications. The proposed algorithm is also described using VHDL and synthesised using Xilinx synthesiser tool in order to implement on field‐programmable gate array (FPGA). The FPGA post route and place implementation results show nearly 90% reduction in resource utilisation and nearly 2.6 times improvement in clock frequency as compared with the existing FPGA based implementation for similar specifications.