Open AccessEfficient ASIC and FPGA implementation of cube architecture
Author(s) -
Barik Ranjan Kumar,
Pradhan Manoranjan
Publication year - 2017
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
ISSN - 1751-861X
DOI - 10.1049/iet-cdt.2016.0043
Subject(s) - field programmable gate array , application specific integrated circuit , computer science , compiler , cube (algebra) , microprocessor , architecture , decimal , gate array , parallel computing , computer hardware , embedded system , computer architecture , arithmetic , mathematics , combinatorics , art , visual arts , programming language
This study presents a generalised architecture for cube operation based on Yavadunam sutra of Vedic mathematics. This algorithm converts the cube of a large magnitude number into smaller magnitude number and addition operation. The Vedic sutra for decimal numbers is extended to binary radix‐2 number system considering digital platforms. The cubic architecture is synthesised and simulated using Xilinx ISE 14.1 software and implemented on various Field‐programmable gate array devices for comparison purpose. The Encounter(R) RTL Compiler RC13.10 v13.10‐s006_1 of cadence tool is also used considering Application specific integrated circuit platform. The performance parameters such as delay, area and power are obtained from synthesis reports. The results show that the proposed architecture is useful for less area and high‐speed application in microprocessor environment.