Open AccessAnalysis and design of moderate inversion based low power low‐noise amplifier
Author(s) -
MM Vinaya,
Paily Roy,
Mahanta Anil
Publication year - 2016
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/iet-cdt.2015.0172
Subject(s) - cascode , low noise amplifier , electronic engineering , subthreshold conduction , noise figure , amplifier , cmos , computer science , electrical engineering , transistor , flicker noise , inversion (geology) , engineering , voltage , paleontology , structural basin , biology
A fully integrated, low power low‐noise amplifier (LNA) is implemented for 2.14 GHz band using 65‐nm radio frequency CMOS technology. By taking advantage of higher transition frequencies of recent technologies, transistors are biased in the moderate inversion region thus permitting scaling down the supply voltage to 0.7 V. Further, the exploration of design spaces from strong to weak inversions assisted the development of a unified noise factor model. An optimisation is carried out based on the parameter extraction and accordingly an extraction methodology is developed. Overall, the unified model based on the parameter extraction helped in noise estimation in all regions of inversion. The resulting LNA achieves a good power match at the input where the simulated S 11 parameter shows an excellent value of −22 dB. Compared to other existing subthreshold cascode LNAs reported in the literature, it shows reasonably better performance in terms of noise and power consumption with a noise figure of 3.74 dB and a moderate power gain of 8.7 dB at a core device current consumption of 450 μA.