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Erratum: ‘Highly adaptive and deadlock‐free routing for three‐dimensional networks‐on‐chip’
Publication year - 2016
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
ISSN - 1751-861X
DOI - 10.1049/iet-cdt.2015.0142
Subject(s) - deadlock , computer science , parallel computing , network on a chip , adaptive routing , chip , routing (electronic design automation) , routing algorithm , computer architecture , distributed computing , embedded system , static routing , routing protocol , telecommunications

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