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Switchable cache: utilising dark silicon for application specific cache optimisations
Author(s) -
Nawinne Isuru,
Javaid Haris,
Ragel Roshan,
Parameswaran Sri
Publication year - 2016
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
ISSN - 1751-861X
DOI - 10.1049/iet-cdt.2015.0114
Subject(s) - cache , cache algorithms , smart cache , parallel computing , computer science , cache coloring , cache invalidation , cache pollution , page cache , cpu cache , computer architecture
Caches are used to improve memory access time and energy consumption. The cache configuration which enables the best performance often differs between applications due to diverse memory access patterns. The authors present a new concept, called switchable cache, where multiple cache configurations exist on chip, leveraging the abundant transistors available due to what is known as the dark silicon phenomenon. Only one cache configuration is active at any given time based on the application under execution, while all other configurations remain inactive (dark). They describe an architecture to enable seamless integration of multiple cache configurations, and a novel design space exploration methodology to rapidly pre‐determine the optimal set of configurations at design‐time, for a given group of applications. For design spaces containing trillions of design points, the authors’ exploration methodology always found the optimal solution in less than 2 s. The switchable cache improved memory access time by up to 26.2% when compared to a fixed cache.

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