Open AccessEvaluating fault tolerance on asymmetric multicore systems‐on‐chip using iso‐metrics
Author(s) -
Chalios Charalampos,
Nikolopoulos Dimitrios S.,
Catalán Sandra,
QuintanaOrtí Enrique S.
Publication year - 2016
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/iet-cdt.2015.0056
Subject(s) - emulation , computer science , multi core processor , embedded system , fault tolerance , frequency scaling , implementation , reliability (semiconductor) , energy consumption , supercomputer , reliability engineering , power (physics) , distributed computing , engineering , parallel computing , electrical engineering , physics , quantum mechanics , economics , programming language , economic growth
The end of Dennard scaling has promoted low power consumption into a first‐order concern for computing systems. However, conventional power conservation schemes such as voltage and frequency scaling are reaching their limits when used in performance‐constrained environments. New technologies are required to break the power wall while sustaining performance on future processors. Low‐power embedded processors and near‐threshold voltage computing (NTVC) have been proposed as viable solutions to tackle the power wall in future computing systems. Unfortunately, these technologies may also compromise per‐core performance and, in the case of NTVC, reliability. These limitations would make them unsuitable for HPC systems and datacenters. To demonstrate that emerging low‐power processing technologies can effectively replace conventional technologies, this study relies on ARM's big.LITTLE processors as both an actual and emulation platform, and state‐of‐the‐art implementations of the CG solver. For NTVC in particular, the study describes how efficient algorithm‐based fault tolerance schemes preserve the power and energy benefits of very low voltage operation.