Open AccessEfficient implementation of bit‐parallel fault tolerant polynomial basis multiplication and squaring over GF(2 m )
Author(s) -
Rashidi Bahram,
Sayedi Sayed Masoud,
Rezaeian Farashahi Reza
Publication year - 2016
Publication title -
iet computers and digital techniques
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.219
H-Index - 46
eISSN - 1751-861X
pISSN - 1751-8601
DOI - 10.1049/iet-cdt.2015.0020
Subject(s) - multiplication (music) , polynomial basis , overhead (engineering) , parallel computing , gf(2) , finite field , computer science , polynomial , basis (linear algebra) , fault tolerance , trinomial , critical path method , path (computing) , comparator , mathematics , arithmetic , discrete mathematics , combinatorics , engineering , mathematical analysis , distributed computing , geometry , programming language , electrical engineering , systems engineering , voltage , operating system
This study presents the design and implementation of an efficient structure for fault tolerant bit‐parallel polynomial basis multiplication and squaring over GF(2 m ), based on a similar strategy of Roving method with a minimum overhead. The Roving method is an efficient method for the circuits in which many similar and independent structures exist. The architectures of the polynomial basis multiplication and squaring over binary finite fields have inherent regularity in their subsections of the structures. Therefore, they are compatible to the applied version of Roving fault tolerant method. To generalise the proposed architecture, the multiplication and squaring operations are examined for different primitive polynomial, including general irreducible polynomials, irreducible pentanomials and irreducible trinomials. In the proposed design, the extracted common circuit has low hardware utilisation compared with that of the main circuit. The fault tolerant circuit is constructed by using three copies of the common circuit, a comparator and a voter circuit. The comparator and voter have parallel architectures with low critical path delays, which is a critical factor in any highly computational system. The design has been successfully verified and synthesised onVirtex‐4 XC4VLX200 FPGA using Xilinx ISE 11. The results show an overall improvement in the speed and hardware usage compared with those of previous designs.